Olimex Showcases Develoment Board Design Based on ESP32-P4 RISC-V SoC

M5Stack has launched the M5Stack LLM Module, an advanced offline large language model inference module designed for terminal devices requiring efficient, cloud-independent AI processing. This product is described as targeting offline applications such as smart homes, voice assistants, and industrial control. The AX630C SoC appears to include dual-core Arm A53 processors clocked at 1.2GHz, along […]

Infineon Technologies XENSIV game controller is a reference design that integrates XENSIV magnetic position sensors for precise joystick control without sensor drift and XENSIV Hall switch triggers for reliable operation. The controller also features capacitive CAPSENSE buttons, CAPSENSE presence detection, and a SPIDER+ rumble driver. These components work together with the PSoC 6 BLE microcontroller to create a low-power, plug-and-play solution. The onboard display allows users to monitor joystick movements, connection status, configurations, and battery information. The controller connects to PCs or smartphones as a USB human interface device (HID) without requiring manual configuration or driver installation. It also supports Bluetooth Low Energy and uses capacitive presence detection to optimize battery life. The design includes a PSoC 6 debugger and supports customizable shields providing flexibility for software and hardware integration. Previously, we covered an Arduino Nano Matter-powered game controller that successfully ported Quake, a popular first-person shooter game. We’ve also [...]

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This report was written by Emmanuel Nyarko as part of Google Summer of Code 2024.

Alternate Queuing has been of great need in the high Performance Computing space since the continuous records of unfair disruption in network quality due to the buffer bloat problem. The buffer bloat problem still persists and not completely gone but modern active queue managements have been introduced to improve the performance of networks.

ALTQ was refactored to basically improve maintainability. Duplicates were handled, some compile time errors were fixed and also performance has been improved too.

This improves the quality of developer experience on maintaining the ALTQ codebase.

The Controlled Delay (CoDel) active queue management has also been integrated into the netbsd codebase. This introduces improvements made in the area of quality of service in the netbsd operating system. CoDel was a research led collaborative work by Van Jacobness and Kathleen Nichols which was developed to manage queues under control of the minimum delay experienced by packets in the running buffer window.

As it stands now, ALTQ in NetBSD is integrated in PF packet filter. I am currently working to integrate it in the NPF packet filter. The code in NetBSD is on the constant pursuit to produce clean and maintainable code.

I'll also be working to improve quality of service in NetBSD through quality and collaborative research driven by randomness in results. As a research computer scientist, I will be working to propose new active queue managements for the NetBSD operating system to completely defeat the long lasting buffer bloat problem.

More details of the work can be found in my Google Summer of Code 2024 work submission.

Altera, an independent subsidiary of Intel, has launched the Altera Agilex 3 SoC FPGA lineup built on Intel’s 7nm technology. According to Altera, these FPGAs prioritize cost and power efficiency while maintaining essential performance. Key features include an integrated dual-core Arm Cortex A55 processor, AI capabilities within the FPGA fabric (tensor blocks and AI-optimized DSP sections), enhanced security, 25K–135K logic elements, 12.5 Gbps transceivers, LPDDR4 support, and a 38% lower power consumption versus competing FPGAs. Built on the Hyperflex architecture, it offers nearly double the performance compared to previous-generation Cyclone V FPGAs. These features make this device useful for manufacturing, surveillance, medical, test and measurement, and edge computing applications. Altera’s Agilex 3 AI SoC FPGA specifications Device Variants B-Series – No definite information is available C-Series – A3C025, A3C050, A3C065, A3C100, A3C135 SoC FPGAs Hard Processing System (HPS) – Dual-core 64-bit Arm Cortex-A55 up to 800 MHz that supports secure [...]

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